Huawei Shifts Focus to Faster Chip Architecture amid US Curbs
Huawei's innovative chip design strategy aimed at enhancing transmission speed instead of further miniaturizing semiconductors provides an opportunity for China to produce advanced chips despite U.S. restrictions, though it is yet to be determined if it signifies a genuine advancement.
Since 2019, China has been prohibited from bringing in ASML's cutting-edge extreme ultraviolet (EUV) lithography equipment, limiting its chip manufacturers' capacity to compete with global frontrunners such as Taiwan's TSMC, which depend on increasingly miniaturized manufacturing methods that enhance chip performance.
For many years, the semiconductor sector has been ruled by Moore's Law - the principle that the transistor count on a microchip approximately doubles every two years.
This week, Huawei presented a different method: reducing the time it takes for signals to travel through chips and extensive computing systems utilizing a principle it refers to as the Tau Scaling Law.
The primary method, LogicFolding, focuses on organizing logic, analog, and memory circuits in compact, vertically integrated configurations, which could enhance density, performance, and clock rates in the coming ten years.
Supporters view it as a method to prolong chip development as manufacturing improvements start to decelerate.
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"Huawei's chips encounter two main limitations." "It is certain that Moore's Law will reach a physical 'wall' in the coming decade," He Tingbo, president of Huawei's semiconductor division, informed China's People's Daily this week.
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"The other is unintentional due to the external limitations that Huawei faced this 'barrier' sooner than its competitors," she noted, probably referring to U.S. sanctions on the import of sophisticated EUV machines.
However, some contend that minimizing latency has consistently been a focus in semiconductor design and that numerous fundamental concepts mirror current efforts in three-dimensional (3D) stacking, advanced packaging, and system optimization.
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TSMC leads with its packaging technology known as SoIC, which allows for more closely integrated heterogeneous chiplets to enhance performance and minimize size.